(1) Field of the Invention
The present invention relates to a data writing circuit for a nonvolatile semiconductor memory such as a flash memory etc., in particular relating to a data writing circuit for a nonvolatile semiconductor memory having a virtually grounded memory cell array.
(2) Description of the Prior Art
As one type of nonvolatile semiconductors, flash memories have been conventionally known in which written data can be electrically erased in whole or in part (in blocks as the units). This flash memory is composed of memory cells for storing one bit of data as a minimum unit, made up of a MOS (metal-oxide-semiconductor) field effect transistor with a floating gate (to be referred to hereinbelow as `memory cell` for simplicity) having a sectional structure as shown in FIG. 1.
Illustratively, the memory cell shown in the figure is produced by selectively diffusing a n-type dopant such as arsenic (atomic symbol: As) or the like onto the principal plane of a semiconductor substrate S of p-type, for example, to form the source S and drain D, and then forming layers of a tunnel oxide film (not coded), a floating gate FG and inter-layer insulating film (not coded) and a control gate CG, in this sequential order, on the substrate principal surface in the channel forming region between the source S and drain D. In the thus configured memory cell, the apparent threshold voltage V.sub.thc of the memory cell is varied by drawing or injecting electrons with respect to the floating gate FG to thereby write or erase data. Hereinbelow, a reference to `transistor` means a field effect transistor.
In the above case, data `0` written in a memory cell corresponds to the state where the threshold voltage V.sub.thc is made high in the memory cell (state where electrons have been injected therein), and data `1` corresponds to the state where the threshold voltage V.sub.thc is made low (state where electrons have been drawn therefrom). Accordingly, when data is erased in whole, all the memory cells are initialized to the data state `0`. When data is written in, all the data is erased and then electrons are drawn from selective floating gates FG from memory cells in which data `1` should be written.
A type of memory cell has been disclosed in, for example, "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" (IEEE, J. Solid-State Circuits, vol.29, No.4. pp.454-460, April 1994) and in "16 Mbit DINOR Flash Memory for 3.3 V single power source" (The Journal of the Institute of Electronics, Information and Communication Engineers, ICD95-38, pp.55-62, 1995). This memory cell uses a type of tunnel current, namely, Fowler-Nordheim Current (to be referred to as `FN current`).
In this memory cell, with respect to the floating gate FD, electrons are drawn through the drain D side by the FN current to selectively write data `1` while electrons are injected through the source S side also by the FN current to erase data `1` (to initialize the cell to data `0`). Conditions of the applied voltages for each operational mode are shown in Table 1.
TABLE 1 ______________________________________ Substrate Operation Control (p-type mode gate Drain Source well) ______________________________________ Program -8 V 4 V/0 V Floating 0 V Erase 10 V Floating -8 V -8 V Read 3 V about 1 V 0 V 0 V ______________________________________
As shown in Table 1, when data `1` is written in to this memory cell, a negative voltage V.sub.nw (e.g. -8 V) is applied to the control gate CG and a positive voltage V.sub.pp, (e.g. +4 V) to the drain D with the source S floating, so that a high electric field reaches from the drain D to the floating gate FG to generate an FN current. Thus, electrons are drawn from the floating gate FG toward the drain D to thereby lower the threshold voltage V.sub.thc of the memory cell to about 1.5 V thus writing data `1`.
When the data `1` thus written in is erased, a positive voltage V.sub.pe (e.g. +10 V) is applied to the control gate CG and a negative voltage V.sub.ns (e.g. -8 V) to the source S with the drain D floating, so that electrons are injected from the source S side and the substrate to the floating gate by the FN current, to thereby increase the threshold voltage V.sub.thc of the memory cell which has been made low, to about 3 V or above, thus initializing the cell to data `0`.
Further, when the written data is read out from the memory cell, a source voltage V.sub.cc (e.g. 3 V) is applied to the control gate CG, a bias voltage V.sub.bias (e.g. 1 V) to the drain D and a ground voltage V.sub.ss (0 V) to the source S, and the drain current I.sub.d flowing through the memory cell is detected and read. That is, when the threshold voltage V.sub.thc of the memory cell is varied by writing data (by drawing or injecting electrons), the drain current I.sub.d flowing through the memory cell varies. Therefore, it is possible to read out the written data by detecting the drain current I.sub.d flowing through the memory cell.
In general, in a flash memory, as shown in FIG. 2, an NOR type cell array is formed of memory cells 00 to nn for which data is written in, read out or erased using the aforementioned FN current. Now, data writing, erasing and reading operations will be explained exemplifying a memory cell 00 as an element of the NOR type cell array shown in FIG. 2.
In this figure, when data `1` is written in to memory cell 00, V.sub.nw (-8 V) is applied to word line WL0, a voltage V.sub.pp (+4 V) to bit line BL0 with common source line SL floating. In this condition, a high electric field is generated which derives from the drain toward the floating gate in memory cell 00 and electrons are drawn from the floating gate toward the drain by the FN current, to thereby lower the threshold voltage of memory cell 00.
When the data to be written is `0`, ground voltage V.sub.ss (0 V), in place of the aforementioned V.sub.pp is applied to bit line BL0. In this case, the electric field between the floating gate and drain in memory cell 00 becomes low, so that no FN current will flow. Accordingly, no electrons are drawn from the floating gate, therefore its threshold voltage V.sub.thc is maintained at 3 V or above (the initialized data `0` is maintained).
Next, when the written data is erased, a positive high voltage V.sub.pe (+10 V) is applied to all the word lines WL0 to WLn (the control gate of each memory cell), a negative voltage V.sub.ns (-8 V) applied to the common source lines SL (the source of each memory cell) and the substrate with all the bit lines BL0 to BLn (the drain of each memory cell) floating. In this setting, in all the memory cells inclusive of memory cell 00, a high electric field is generated between the source, or the substrate, and the floating gate, so that electrons are injected into each floating gate FG. As a result, the threshold voltages for all the memory cells are increased so that each memory cell reverts to the initialized state or the state of data `0`.
Next, when the data is read out from memory cell 00 (inclusive of the case of verification), a read bias voltage V.sub.bias (about 1 V) is applied to bit line BL0, ground voltage V.sub.ss (0 V) to the common source line SL, and V.sub.cc (3 V) to word line WL0, to detect the drain current I.sub.d. In this detection, if the drain current I.sub.d is high, the data is read out from the memory cell as it is judged to be `1`, whereas if the drain current I.sub.d is low, the data is judged to be data `0`.
Referring now to FIG. 3, explanation will be made of a conventional data writing circuit for writing data into memory cells constituting of the aforementioned NOR type cell array. A conventional data writing circuit 100 shown in this figure, is composed of a transfer gate TG for selecting a bit line BL connected to the drain of a memory cell M in accordance with a column selection signal Y given from an unillustrated decoder and a latch circuit L connected to the bit line BL via this transfer gate TG. This latch circuit L is a flip-flop composed of two inverters (not coded) with their inputs and outputs cross-coupled with each other. The power source for these inverters (the flip-flop) is switched between voltage V.sub.pp (e.g. +4 V) and the power source voltage V.sub.cc (e.g. +3 V) in accordance with the operation mode.
Now, when data `1` is written in to the memory cell M shown in FIG. 3, first the power voltage V.sub.cc (+3 V) is set as the power source for the inverters forming latch circuit L, so as to latch data `1` supplied from an unillustrated data driver. Next, when the power source to the inverters is changed to the voltage V.sub.pp (+4 V) and the transfer gate TG is turned on, a voltage in accordance with the data which has been latched by latch circuit L is applied to bit line BL.
In this case, the data which has been latched by latch circuit L is `1`, so that node A of the flip-flop becomes stabilized at voltage V.sub.pp (+4 V). In this state, if the column selection signal Y given to the gate of transfer gate TG is boosted, this transfer gate TG, without undergoing any voltage drop due to its threshold voltage, transfers the voltage at node A to bit line BL. Accordingly, voltage V.sub.pp (+4 V) at node A of the flip-flop is applied as it is to bit line BL. When the data which has been latched by latch circuit L is `0`, the potential at node A becomes stabilized to ground voltage V.sub.ss (0 V), which in turn is applied to bit line BL.
In this way, the voltage to be applied to bit line BL is selected in accordance with the data to thereby determine the intensity of the electric field between the floating gate and drain in the memory cell. As a result, if this electric field is strong, electrons are drawn and data `1` will be recorded into the cell, whereas, if this electric field is weak, no extraction of electrons will occur, and record data `0` will be recorded (the initial data `0` is maintained).
In the aforementioned NOR type cell array shown in FIG. 2, all the source terminals from memory cells 00 to nn are connected to common source line SL, which needs its wiring area inside the cell array. This is an obstacle to reducing the area of the memory array.
To deal with this, for an NOR type cell array having such a common source line, there is a configuration as shown in FIG. 4, called a virtually grounded cell array, in which the aforementioned common source line SL is eliminated by connecting the drain of one cell to the source of the adjacent cell with a common bit line between the adjacent memory cells. This configuration has been adopted for some EPROMs (erasable programmable ROMs) etc.
Now, this virtually grounded cell array shown in FIG. 4 will be explained. When such a virtually grounded cell array is applied to a flash memory, the memory cell needs to have at least the following characteristics: That is, in the memory cell, the data needs to be written in using a first voltage relationship between the control gate and one of either the drain or source, and the memory cell needs to be insensitive to a second voltage relationship between the control gate and the other of the drain or source except for the readout operation. In this case, `source` here is the one defined based on the voltage application conditions at the time of data readout.
One example of a memory cell having these characteristics, is sectionally shown in FIGS. 5A and 5B. The memory cell shown in the figures has a low dopant concentration on the source side in proximity to the channel forming area and a high dopant concentration on the drain side in proximity thereto. In a memory cell having such a structure, as a result of the difference in dopant concentration between the s ource and the drain, the depletion region formed is greater when, for example, 4 V is applied to the source than when the same voltage, i.e., 4 V is applied to the drain, as shown in FIG. 5B. For this reason, no overlap area appears because of the formation of the depletion layer between the floating gate and the source, and consequently, the electric field therebetween is reduced, to thereby inhibit the generation of the FN current.
As shown in the same figure, on the drain side where the dopant concentration is high, the development of the depletion region is inhibited. Accordingly, an overlap area is generated between the floating gate and the source, so that a high electric field is generated therebetween causing the FN current. Thus, in the case of the memory cell shown in FIGS. 5A and 5B, no electrons are drawn from the source side. This means that the cell presents the property of insensitiveness to the voltage relationship between the control gate and the source with respect to the writing operation. Here, when the distribution relationship of the dopant concentration in the source and drain is reversed, it is possible to create a cell which is insensitive to the voltage relationship between the control gate and the drain with respect to the writing operation.
Another memory cell presenting similar characteristics to that shown in FIGS. 5A and 5B, is shown in FIG. 5C. The memory cell in this figure, has a high dopant density in both the source and the drain with the thickness of the gate oxide film on the drain side formed thinner than that on the source side. In this way, by varying the film thickness of the gate oxide film between the source side and the drain side, it is possible to selectively enhance only the electric field between the drain and the floating gate, thus making it possible to obtain a memory cell which is insensitive to the voltage relationship between the control gate and the source with respect to the writing operation.
Table 2 shows the conditions of the application voltages to the memory cell in FIGS. 5A and 5B in different operation modes.
TABLE 2 ______________________________________ Substrate Operation Control (p-type mode gate Drain Source well) ______________________________________ Program -8 V 4 V/* 4 V/* 0 V Erase 10 V -8 V -8 V -8 V Read 3 V 0 V 1 V 0 V ______________________________________ *Floating or about 1 V
Next, description will be made of the operation of writing data into a virtually grounded cell array shown in FIG. 4 composed of memory cells having the above characteristics. Concerning a symbol of the memory cells shown in FIG. 4, the node with an oblique line corresponds to the source (the region with a low dopant concentration) in FIG. 5B.
Generally, in the case of a flash memory which uses the FN current for its writing operation, in order to reduce the time for writing, so-called multi-byte write method is used which allows simultaneous writing operations to a plurality of memory cells connected to a single word line. Therefore, the voltage to each of bit lines BL0 to BLn during writing is applied in accordance with the type of data to be written into the memory cell which is connected to the bit line.
However, in this case, differing from the case of the aforementioned NOR type cell array, the writing voltage applied to the bit lines to which the drain of the memory cell to be written in with data `0` is connected, needs to be set at the state of floating or at about +1 V, instead of voltage V.sub.ss (0 V) in order to avoid inhibiting the adjacent cell from being written in with data `1`. This will be detailed later.
Now, referring to Table 2 showing conditions of application voltages in different operational modes, the write, erase and read operations for memory cell 00 shown in FIG. 4 will be described. First, when data `1` is written in to memory cell 00, a negative voltage V.sub.nw (e.g. -8 V) is applied to word line WL0 (the control gate in the memory cell) and a positive voltage V.sub.pp (e.g. +4 V) to bit line BL0 (the drain in the memory cell). At this moment, applied to the source of memory cell 00, or bit line BL1 is voltage V.sub.pp (+4 V) when the data to be written into the adjacent memory cell 01 is `1`, whereas the floating state or about 1 V is set up for the case of data `0` (it should be noted that this is not voltage V.sub.ss (0 V)).
When memory cell 00 is biased under such write voltage conditions, the aforementioned FN current flows between the floating gate and drain so that electrons are drawn from the floating gate toward the drain side. As a result, threshold voltage V.sub.thc of memory cell 00 lowers, and hence data `1` is written in to the memory cell 00. However, at this moment, if the voltage V.sub.ss (0 V) is applied without the source being floating, sufficient quantity of electrons cannot be drawn from the floating gate, and hence a phenomenon occurs that data `1` cannot be written in.
Now, this phenomenon will be explained with reference to FIG. 6. FIG. 6 shows the dependence of the threshold voltage of the memory cell upon the time for writing data `1` when the source voltage is taken as a parameter with the drain voltage set at 4 V. As seen from the chart, concerning the write characteristics of the memory cell, the threshold voltage lowers more slowly and hence the time for writing data `1` becomes longer when the source voltage is set at 0 V than when the source is set at +1 V or is set at floating.
The cause of this phenomenon resides in that as a result of extracting electrons from the floating gate in order to write data `1`, the potential of the floating gate will rise and hence threshold voltage V.sub.thc will lower. Actually, when threshold voltage V.sub.thc lowers due to the extraction of electrons from the floating gate, a channel is formed between the drain and source in the memory so that current flows therebetween. Thus the potential at the drain lowers under the influence of the source side. As a result, the electric field between the drain and the floating gate is reduced, which inhibits the FN current (the reduction of threshold voltage V.sub.th is inhibited), thereby the time for writing data `1` becomes longer. In the worst case, the threshold voltage of the memory cell cannot be lowered to a prescribed level that allows the distinction of data `1`, or it becomes impossible to write data `1` normally.
In contrast, in the case where the source of the memory cell is set at floating, when electrons are drawn from the floating gate and a channel is formed allowing current to flow from the drain to the source, the source potential gradually increases. With this increase in the source potential, the potential at the control gate relatively lowers, and this inhibits the current from the drain to the source. This current inhibition in combination with an extra effect, namely, the back gate effect due to the increase of the source potential, will block the channel in the memory cell. When the channel in the memory cell shuts down, the drain potential restores to its original state, so that a high electric field is produced between the drain and the floating gate, thus allowing the normal writing of data `1`.
Further, in this case, if the source is biased with a voltage, e.g. about +1 V, instead of setting the source of the memory cell at the floating state, the back gate effect is effective from the start of the write operation, thereby efficiently inhibiting a channel from forming. Therefore, it is possible to prevent the reduction in the drain voltage from the beginning of the write operation. Accordingly, in this case, it is possible to write data `1` in a shorter time.
Next, when data `0` is written in to the memory cell 00 shown in FIG. 4 (in this case, the memory cell 00 is assumed to be initialized), bit line BL0 is set at the floating state (or at about +1 V). Here, the potential at BL1 is set at voltage V.sub.pp (+4 V) or at the floating state (or about +1 V) in accordance with the data to be written into the memory cell 01. As the reason already mentioned, application of ground voltage V.sub.ss (0 V) to the bit line is prohibited.
In this case, even if, in order to write data `1` to the adjacent memory cell 01, voltage V.sub.pp (+4 V) is applied to bit line BL1 to which the source of memory cell 00 is connected, no electrons are drawn from the floating gate of memory cell 00 toward the source (bit line BLI) side because the write characteristics of the memory cell is set to be insensitive to the voltage on the source side. That is, the operation of writing data `0` to memory cell 00 will not be affected by the write operation to memory cell 01.
Next, when data is retrieved from memory cell 00, basically, similar bias conditions to that in a conventional NOR type array are set up. Specifically, V.sub.cc (+3 V) is applied to word line WL0 (control gate), V.sub.bias (+1 V) to bit line BL0 (drain), and V.sub.ss (0 V) to bit line BL1 (source). In this setup, the drain current I.sub.d is detected so as to read the data out.
Next, when the data written in the memory cell is eased, a positive high voltage V.sub.pe (e.g. +10 V) is applied to all the word lines WL0 to WLn, and a negative voltage V.sub.ns (e.g. -8 V) is applied to all the bit lines BL0 to 0n and to the substrate, so that electrons are as a whole injected into individual floating gates of all the memory cells 00 to nn through the drain and substrate region by the FN current. As a result, in each memory cell, the threshold voltage is increased to about 3 V or more, which means the initialization or the state of data `0`.
However, when the conventional circuit 100 shown in FIG. 3 is used as the data writing circuit for writing data into the memory cells constituting the aforementioned virtually grounded cell array, when ground voltage V.sub.ss (0 V) must be applied to the bit line to write data `0`. This causes the problem as stated above in that it becomes impossible to write data `1` into the memory cells whose source is connected to this bit line.